Analog Devices SHARC ADSP-21368 - Timing External Memory Accesses

SDRAM Controller
3-36 ADSP-21368 SHARC Processor Hardware Reference
tRC
Required delay between issuing successive bank activate commands to the
same SDRAM internal bank. This delay is not directly programmable.
The t
RC
delay is satisfied by programming the SDTRAS and SDTRP fields to
ensure that t
RAS
+ t
RP
≥ t
RC
.
tRFC
Required delay between issuing an auto-refresh command and a bank acti-
vate command, and between issuing successive auto-refresh commands.
This delay is not directly programmable and is assumed to be equal to t
RC
.
The t
RC
delay is satisfied by programming the SDTRAS and SDTRP fields to
ensure that t
RAS
+ t
RP
≥ t
RC
.
tRRD
This is the required delay between a bank A activate command and a bank
B activate command. This delay is not programmable and fixed to
t
RCD
+ 1 cycles. This delay is used for multibank operation (ADSP-2137x
processors only).
tXSR
Required delay between exiting the self-refresh mode and issuing an
auto-refresh command. This delay is not directly programmable and is
assumed to be equal to t
RC
. The t
RC
delay is satisfied by programming the
t
RAS
and t
RP
fields to ensure that t
RAS
+ t
RP
≥ t
RC
.
Timing External Memory Accesses
The SDRAM controller is capable of running at up to 166 MHz and can
run at various frequencies, depending on the programmed SDRAM clock
(
SDCLK) to core clock (CCLK) ratios. These are shown in Table 3-13.