ADSP-21368 SHARC Processor Hardware Reference 3-35
External Port
tRAS
Required delay between issuing a bank activate command and a precharge
command, and between issuing the self-refresh command and the exit
from self-refresh mode. The
SDTRAS bits (7–4) in the SDCTL register can be
set to 1 to 15 clock cycles.
tRP
Required delay between issuing a precharge command and issuing:
• a bank activate command
• an auto-refresh command
• a self-refresh command
The SDTRP bits (10–8) in the SDCTL register can be set to 1 to 7 clock
cycles.
tMRD
Required delay between issuing a mode register set command and a suc-
cessive bank activate command. This delay is not directly programmable
and is assumed to be 2 clock cycles.
tRCD
Required delay between a bank activate command and the start of the first
read or write command. The
SDTRCD bits (26–24) in the SDCTL register can
be set to 1 to 7 clock cycles.
tWR
Required delay between a write command (driving write data) and a pre-
charge command. The SDTWR bits (18–17) in the SDCTL register can be set
to 1 to 3 clock cycles.
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