SDRAM Controller
3-34 ADSP-21368 SHARC Processor Hardware Reference
The initial read or write triggers the SDRAM power-up sequence, which
programs the SDRAM’s mode register with the CAS latency from the
SDCTL register. This initial read or write to SDRAM takes many cycles to
complete. Note that for most applications the SDRAM power-up
sequence and a write to the mode register is performed only once. Once
the power-up sequence has completed, the SDPSS bit should not be set
again unless a change to the mode register is desired.
Page size
Page size is the amount of memory which has the same row address and
can be accessed with successive read or write commands without needing
to activate another row.
Precharge command
The precharge command closes a specific internal bank in the active page
or all internal banks in the page. For more information, see “SDC Com-
mands” on page 3-63.
Self-refresh
When the SDRAM is in self-refresh mode, its internal timer initiates
auto-refresh cycles periodically, without external control input. The SDC
must issue a series of commands, including the self-refresh command, to
put the SDRAM into this low power mode. It must issue another series of
commands to exit self-refresh mode. Entering self-refresh mode is pro-
grammable in the SDRAM control register (
SDCTL) and any access to the
SDRAM address space causes the SDC to exit the SDRAM from
self-refresh mode. For more information, see “Self-Refresh Mode” on
page 3-70.
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