ADSP-21368 SHARC Processor Hardware Reference 3-33
External Port
CBR (CAS before RAS)
Refresh or auto-refresh. When the SDC refresh counter times out, the
SDC precharges all four banks of SDRAM and then issues an auto-refresh
command to them. This causes the SDRAMs to generate an internal CBR
refresh cycle. When the internal refresh completes, the SDRAM banks are
precharged.
Data mask feature
SDRAM’s allow partial read or writes in byte addressing mode. Since
SHARC processors do not support byte addressing,
DQM pins are not con-
trolled by the SDC.
Internal bank
There are several internal memory banks on a given SDRAM row. An
internal bank in a specific row cannot be activated (opened) until the pre-
vious internal bank in that row has been precharged.
The SDC does not support multibank accesses. The bank address can be
thought of as part of the row address. The SDC also assumes that all
SDRAMs to which it interfaces have four internal banks.
L
Only the SDRAM controller on the ADSP-2137x processors sup-
ports multibank accesses.
Mode register
SDRAM devices contain an internal configuration register which allows
specification of the SDRAM device’s functionality. During power-up, and
before executing a read or write to the SDRAM memory space, the appli-
cation must trigger the SDC to write to the SDRAM’s mode register. The
write of the this register is triggered by writing a 1 to the
SDPSS bit (bit 14)
in the processor’s SDRAM control register (SDCTL), and then issuing a
read or write transfer to the SDRAM address space.
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