SDRAM Controller
3-32 ADSP-21368 SHARC Processor Hardware Reference
Burst length
The burst length determines the number of words that the SDRAM device
stores or delivers after detecting a single write or read command,
respectively.
The SDC supports burst length = 1 mode only.
Burst stop command
Use of this command is one of several ways to terminate or interrupt a
burst read or write operation. Since the burst length is hardwired to 1, the
SDC does not support the burst stop command. However, this command
is optionally supported by ADSP-2137x processors.
Burst type
The burst type determines the address order in which the SDRAM deliv-
ers burst data after detecting a read command, or stores burst data after
detecting a write command.
Since the burst length is always programmed to 1, the burst type does not
apply. However, the SDC always sets the burst type to sequen-
tial-accesses-only during the SDRAM power-up sequence.
CAS latency
Also t
AA
, t
CAC
. The column address strobe (CAS) latency is the delay in
clock cycles between when the SDRAM detects the read command and
when it provides the data at its output pins. The CAS latency is pro-
grammed in the SDRAM mode register during the power-up sequence
with the value programmed in the SDRAM control register (SDCTL bits
1-0).
The speed grade of the SDRAM and the SDCLK frequency determine the
value of the CAS latency. The SDC supports CAS latencies of 2 or 3 clock
cycles. The selected CAS latency value is programmed into the
SDCTL reg-
ister before the SDRAM power-up sequence.
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