Shared Memory Interface
3-88 ADSP-21368 SHARC Processor Hardware Reference
When
BCNT decrements to zero, the bus master first completes its off-chip
read/write and then deasserts its own BRx (any new off-chip accesses are
delayed), which allows transfer of bus mastership. If the ACK signal is hold-
ing off an access when BCNT reaches zero, bus mastership is not
relinquished until the access can complete.
If BCNT reaches zero while bus lock is active, the bus master does not deas-
sert its BRx line until bus lock is removed. Bus lock is enabled by the BUSLK
bit (bit 29 of SYSCTL register). For more information, see “Bus Lock and
Semaphores” on page 3-92.
Bus Synchronization After Reset
When a shared memory system comes out of reset (after RESET is asserted),
the bus arbitration logic on each processor must synchronize, ensuring
that only one processor drives the external bus. One processor must
become the bus master, and all other processors must recognize it before
actively arbitrating for the bus. The bus synchronization scheme also lets
the system safely bring individual processors into and out of reset.
One of the processors in the system must be assigned ID = 001 in order for
the bus synchronization scheme to function properly. This processor also
holds the external bus control lines stable during reset.
L
Bus arbitration and synchronization are disabled if the processor is
in a single processor system (
ID = 000).
Figure 3-17. BMAX Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
BMAX = maximum # of bus
mastership cycles – 2
Bits 31-16 are reserved.
BMAX (0x180D)
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