ADSP-21368 SHARC Processor Hardware Reference 3-89
External Port
To synchronize their bus arbitration logic and define the bus master after
a system reset, the multiple processors obey the following rules:
• All processors except the one with
ID = 001 deassert their BRx line
during reset. They keep their BRx deasserted for at least two cycles
after reset and until their bus arbitration logic is synchronized.
• After reset, a processor considers itself synchronized when it detects
a cycle in which only one BRx line is asserted. The processor identi-
fies the bus master by recognizing which BRx is asserted and
updates its internal record to indicate the current master.
• The processor with ID = 001 asserts its BRx during reset and for at
least two cycles after reset. If no other BRx lines are asserted during
these cycles, the processor with ID = 001 drives the memory control
signals to prevent glitches. Although the processor with ID = 001 is
asserting its BRx and driving the memory control signals during
these cycles, this processor does not perform reads or writes over
the bus.
• While in reset, the processor with ID = 001 attempts to gain con-
trol of the bus by asserting BR1.
• While in reset, the processor with ID = 001 drives the RD, WR, and
MS3-0 signals only if it determines that it has control of the bus. For
the processor to decide it has control of the bus: 1) its
BR1 signal
must be asserted and 2) in the previous cycle, no other processor’s
BRx signals were asserted.
The processor with ID = 001 continues to drive the RD, WR, and MS3-0 sig-
nals for two cycles after reset, as long as other
BRx lines are asserted.
If the processor with ID = 001 is synchronized by the end of the two cycles
following reset, it becomes the bus master. If it is not synchronized at this
time, it deasserts its BRx and stops driving the memory control signals and
does not arbitrate for the bus until it becomes synchronized. When a pro-
cessor has synchronized itself, it sets the
BSYN bit in the SYSTAT register.
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