Shared Memory Interface
3-90 ADSP-21368 SHARC Processor Hardware Reference
If one processor comes out of reset after the others have synchronized and
started program execution, that processor may not be able to synchronize
immediately (for example, if it detects more than one
BRx line asserted). If
the non-synchronized processor tries to execute an instruction with an
off-chip read or write, it cannot assert its BRx line to request the bus and
execution is delayed until it can synchronize and correctly arbitrate for the
bus.
During reset, the ACK line is pulled high internally by the processor bus
master with a 20 kΩ equivalent resistor.
In a system where multiple ADSP-21368 processors share a bank of
SDRAM, the master processor’s SDRAM controller powers up the
SDRAM. The master processor then periodically performs an auto-refresh
command as expected. When another ADSP-21368 arbitrates for and
receives bus mastership, it assumes the responsibility for performing a pre-
charge all command, followed by the auto-refresh command.
When a processor (other than the one responsible for power-up) receives
bus mastership for the first time, the auto-refresh command is not per-
formed. This can cause a delay of up to four times the value programmed
between the execution of auto-refresh commands. Further, this delay can
occur for each processor (other than the master) in the system.
To compensate for this delay, use the following procedure.
1. The processors, other than the one responsible for power-up,
should wait for SDRAM power-up to complete. Flags or NOP-loops
may be used to accomplish this.
2. After detecting that power-up is complete, and before performing
any external data accesses, the processors (other than the power-up
processor) should execute the following set of instructions to
ensure that an auto-refresh command is executed.
r0 = dm(sdram_addr); /* dummy access to grab the bus */
if not BM jump(pc,0); /* wait for bus mastership */
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