UART Control and Status Registers
A-118 ADSP-21368 SHARC Processor Hardware Reference
UART Control and Status Registers
The processor provides a set of PC-style, industry-standard control and
status registers for each UART. These memory-mapped registers (MMRs)
are byte-wide registers that are mapped as half-words with the most signif-
icant byte zero-filled. Transmit and receive channels are buffered. The
UARTxTHR register buffers the transmit shift register (UARTxTSR) and the
UARTxRBR register buffers the receive shift register (UARTxLSR). The shift
registers are not directly accessible by software.
Line Control Registers (UARTxLCR)
The UART line control registers (UARTxLCR, shown in Figure A-48) con-
trol the format of received and transmitted character frames. The UARTSB
bit functions even when the UART clock is disabled. Since the transmit
pin normally drives high, it can be used as a flag out pin, if the UART is
not used. In 9-bit mode, the word length is always 8 and the 9th bit is
transmitted instead of the parity bit.
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