ADSP-21368 SHARC Processor Hardware Reference I-1
IINDEX
Numerics
128-channel TDM, 5-4
16-bit to 32-bit word packing enable
(PACK), 5-62
16-bit word lengths, 5-45, 6-32, 7-14
32-bit word lengths, 5-45, 6-32, 7-14
8-bit word lengths, 6-31
A
accessing IOP registers, latency in, 2-3
accuracy, PWM, 8-17
ACK (acknowledge) signal, 3-2, 3-19, 3-21
acknowledge (ACK) pin, 3-20
activate command, bank, 3-31
active low frame sync select for frame sync
(INVFSx) bit, 13-12
active low versus active high frame syncs,
5-39
active state multichannel receive frame sync
select (LMFS) bit, 5-29
AD1855 stereo DAC
power down, 6-7
address
column, row and bank address mapping
(32-bit), 3-53
core to external memory, 3-52
decoding address bank, 3-53
row in SDRAM, 3-34
SDRAM (external memory space), 3-52
SPORT IOP (listing), 5-50
address bus (ADDR) pin, 3-20, 3-83
addressing, 14-53
7-bit in TWI, 12-1, 12-15
general call in TWI, 12-14
IOP, 2-29
pre-modify, 2-39
restrictions on external memory, 3-3
transfer phase in TWI, 12-6
AMI
See also external port, SDRAM
controller, shared memory
ADDR23-0 bits, 3-28
control (AMICTLx) register, 3-25, A-17
to A-19
DMA, 3-20
hold cycles, 3-23
idle cycle, 3-22
memory bank support, 3-28
modes, setting, 3-24
most significant word first (MSWF) bit,
3-25
packing data (PKDIS) bit, 3-25
read/write throughput, 3-28
reading external memory, 3-25
receive (AMIRX) register, 3-25
signals, 3-20
status (AMISTAT) register, A-20
unpacking data, 3-27
wait states, 3-21
writing external memory,
3-26
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