ADSP-21368 SHARC Processor Hardware Reference 2-39
I/O Processor
as the external index and is incremented by the external modifier
register (
EMEP) after each write. These writes are circular buffered if
circular buffering is enabled.
2. In chained DMA, when the writes are complete, (ICEP = zero) the
EPEI register, which serves as the write pointer of the delay line, is
written back to the internal memory location from where it was
fetched.
3. Reads from external memory. For reads, the tap list (TL) modifiers
are used and the number of reads is determined by the external port
read count register (RCEP). The write pointer in the external port
external index register (EIEP) serves as the index address for these
reads (reads start from where writes end). The EIEP register, along
with tap list modifiers, are used in a pre-modify addressing mode
to create the external address for the writes. For each 32-bit read
the external index is:
• EIEP – TL[0] is the first read address (where TL[0] is the
first tap list entry in internal memory as pointed to by the
external port tap list pointer register TPEP).
• EIEP – TL[1] is the second address, and so on.
Therefore, for each read, the DMA controller fetches the external
modifier from the tap list and the reads are circular buffered (if
enabled).
L
The external address generation follows pre-modify addressing for
reads in delay line DMA and therefore EIEP values are not modi-
fied. Also the
EMEP register does not have any effect during delay
line reads.
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