ADSP-21368 SHARC Processor Hardware Reference 7-15
Input Data Port
FIFO Control and Status
Several bits can be used to control and monitor FIFO operations:
• IDP Enable. The IDP_ENABLE bit (bit 7 of the IDP_CTL0 register)
enables the IDP. This is a global control bit. This bit and the corre-
sponding IDP channel enable bit (IDP_ENx) in the IDP_CTL1
register must be set for data from a channel to get into the FIFO.
• IDP Buffer Hang Disable. The IDP_BHD bit (bit 4 in the IDP_CTL0
register) determines whether or not the core hangs on reads when
the FIFO is empty.
• Number of Samples in FIFO. The IDP_FIFOSZ bits (bits 31–28 in
the DAI_STAT register) monitor the number of valid data words in
the FIFO.
• FIFO Overflow Status. The SRU_OVFx bits in the DAI_STAT register
monitor the overflow error conditions in the FIFO for each of the
channels.
• FIFO Overflow Clear. The IDP_CLROVR bit (bit 6 of the IDP_CTL0
register) clears an indicated FIFO overflow error.
To enable the IDP, two separate bits in two different registers must be set.
The first is the
IDP_ENABLE bit in the IDP_CTL0 register and the second is
the specific channel enable bit which is located in the
IDP_CTL1 register.
When these bits are set (= 1), the IDP is enabled. When these bits are
cleared (= 0), the IDP is disabled, and data cannot come to the
IDP_FIFO
register from the IDP channels. When the IDP_ENABLE bit transitions from
1 to 0, all data in the IDP FIFO is cleared. Writing a 1 to bit 31 of the
IDP_CTL1 register also clears the FIFO. This is a write-only bit and always
returns a zero on reads.
The
IDP_BHD bit is used for buffer hang disable control. When there is no
data in the FIFO, reading the
IDP_FIFO register causes the core to hang.
This condition continues until the FIFO contains valid data. Setting the
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