ADSP-21368 SHARC Processor Hardware Reference 2-13
I/O Processor
• Bit definitions for the
SPIDMAC register are illustrated in “SPI Port
Status (SPISTAT, SPISTATB) Registers” on page A-56.
• Bit definitions for the SPMCTLx register are illustrated in “SPORT
Multichannel Control Registers (SPMCTLx)” on page A-40.
• Bit definitions for the DAI_STAT register are illustrated in
Figure A-41 on page A-110.
Note that there is a one-cycle latency between a change in DMA channel
status and the status update in the corresponding register.
DMA Controller Operation
There are two methods you can use to start DMA sequences: chaining and
non-chaining.
Non-chained DMA. To start a new DMA sequence after the current one
is finished, a program must first clear the DMA enable bit, write new
parameters to the index, modify, and count registers, then set the DMA
enable bit to re-enable DMA.
Chained DMA. Chained DMA sequences are a set of multiple DMA
operations, each autoinitializing the next in line. To start a new DMA
sequence after the current one is finished, the IOP automatically loads
new index, modify, and count values from an internal memory location
pointed to by that channel’s chain pointer register. Using chaining, pro-
grams can set up consecutive DMA operations and each operation can
have different attributes.
L
Chaining is only supported on the SPI and SPORT DMA chan-
nels. The IDP port does not support chaining.
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