Analog Devices SHARC ADSP-21368 User Manual

SRC Operation
10-12 ADSP-21368 SHARC Processor Hardware Reference
differences in their ratios from 0 to 4 f
S_OUT
period counts. The
f
S_OUT
/f
S_IN
ratio adjusts the filter length of the SRC, which corresponds
directly with the group delay. Thus, the magnitude in the phase difference
depends upon the resolution of the f
S_OUT
and f
S_IN
counters. The
greater the resolution of the counters, the smaller the phase difference
error.
Group Delay
When multiple SRCs are used with the same serial input port clock and
the same serial output port clock, the hysteresis causes different group
delays between multiple SRCs. The filter group delay of the SRC is given
by the equations:
SRC Operation
The following sections provide details on the SRC’s operation within the
ADSP-21367/8/9 and ADSP-2137x processors.
L
The maximum data that is transferred through the SRCs is 24-bit.
When 32-bit clock and data is provided to the 128 dB SRC, the
least significant 8-bits are zero. However for a 140 dB SRC, the
least significant 8-bits contain the ratio information. This informa-
tion should be considered while interfacing the SRC to interfaces
such as the S/PDIF.
GDS
16
f
S_IN
--------------
32
f
S_IN
-------------- onds for f
S_OUT
f
S_IN
>
sec+=
GDS
16
f
S_IN
--------------
32
f
S_IN
--------------
⎝⎠
⎛⎞
f
S_IN
f
S_OUT
---------------------
⎝⎠
⎜⎟
⎛⎞
× onds for f
S_OUT
f
S_IN
<
sec+=

Analog Devices SHARC ADSP-21368 Specifications

General

Brand	Analog Devices
Model	SHARC ADSP-21368
Category	Computer Hardware
Language	English