ADSP-21368 SHARC Processor Hardware Reference 10-11
Asynchronous Sample Rate Converter
The digital-servo loop is implemented with a multi-rate filter. To settle
the digital-servo loop filter quickly at startup or at a change in the sample
rate, a fast mode has been added to the filter. When the digital-servo loop
starts up or the sample rate is changed, the digital-servo loop kicks into
fast mode to adjust and settle on the new sample rate. Upon sensing the
digital-servo loop settling down to some reasonable value, the digital-servo
loop kicks into normal or slow mode. During fast mode, the
MUTE_OUT sig-
nal of the SRC is asserted to remind the user to mute the SRC which
avoids clicks and pops.
The FIR filter is a 64-tap filter in the case of f
S_OUT
< f
S_IN
and is
(f
S_IN
/f
S_OUT
) × 64 taps for the case when f
S_IN
> f
S_OUT
. The FIR filter
performs its convolution by loading in the starting address of the RAM
address pointer and the ROM address pointer from the digital-servo loop
at the start of the f
S_OUT
period. The FIR filter then steps through the
RAM by decrementing its address by 1 for each tap, and the ROM
pointer increments its address by the (f
S_OUT
/f
S_IN
) × 2
20
ratio for
f
S_IN
> f
S_OUT
or 2
20
for f
S_OUT
< f
S_IN
. Once the ROM address rolls
over, the convolution is complete. The convolution is performed for both
the left and right channels, and the multiply/accumulate circuit used for
the convolution is shared between the channels.
The f
S_IN
/f
S_OUT
sample rate ratio circuit is used to dynamically alter the
coefficients in the ROM for the case when f
S_IN
> f
S_OUT
. The ratio is
calculated by comparing the output of an f
S_OUT
counter to the output of
an f
S_IN
counter. If f
S_OUT
> f
S_IN
, the ratio is held at one. If f
S_IN
>f
S_OUT
, the sample rate ratio is updated if it is different by more than
two f
S_OUT
periods from the previous f
S_OUT
to f
S_IN
comparison. This is
done to provide some hysteresis to prevent the filter length from oscillat-
ing and causing distortion.
However, the hysteresis of the f
S_OUT
/f
S_IN
ratio circuit can cause phase
mismatching between two SRCs operating with the same input and out-
put clocks. Since the hysteresis requires a difference of more than two
f
S_OUT
periods to update the f
S_OUT
/f
S_IN
ratio, two SRCs may have
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