Precision Clock Generator Registers
A-160 ADSP-21368 SHARC Processor Hardware Reference
PCG Frame Synchronization Registers
(PCG_SYNCx)
These registers, shown in Figure A-77, and Figure A-78 and described in
Table A-67 and Table A-68, allow programs to synchronize the clock
frame syncs units with external frame syncs. For more information, see
“Frame Sync” on page 13-8.
Figure A-77. PCG_SYNC Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0000000000000000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
PCG_SYNC (0x24C5)
Enable synchronization of
FSB with external LRCLK
FSB_SYNC
FSA_SOURCE_IOP
Enable frame sync A input source.
0 = XTAL buffer output selected for frame sync A
1 = EXT_CLKA_I selected for frame sync A
Enable synchronization of
FSA with external LRCLK
FSA_SYNC
Enable synchronization of clock
A with external LRCLK
CLKA_SYNC
CLKA_SOURCE_IOP
Enable clock A input source.
0 = XTAL buffer output selected for clock A
1 = EXT_CLKA_I selected for clock A
Enable synchronization of
clock B with external LRCLK
CLKB_SYNC
FSB_SOURCE_IOP
CLKB_SOURCE_IOP
Enable clock B input source.
0 = XTAL buffer output selected for clock B
1 = EXT_CLKA_I selected for clock B
Enable frame sync B input source.
0 = XTAL buffer output selected for frame sync B
1 = EXT_CLKA_I selected for frame sync B
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