Analog Devices SHARC ADSP-21368 - Page 809

ADSP-21368 SHARC Processor Hardware Reference A-161
Register Reference
Table A-67. PCG_SYNC Register Bit Descriptions
Bit Name Description
0FSA_SYNC Enable synchronization of frame sync A with external
frame sync.
0 = Frame sync disabled
1 = Frame sync enabled
1 CLKA_SYNC Enable synchronization of clock A with external frame
sync.
0 = Clock disabled
1 = Clock enabled
2CLKA_SOURCE_IOPEnable clock A input source.
0 = XTAL buffer output selected for clock A
1 = EXT_CLKA_I selected for clock A
3FSA_SOURCE_IOPEnable frame sync A input source.
0 = XTAL buffer output selected for frame sync A
1 = EXT_CLKA_I selected for frame sync A
16 FSB_SYNC Enable synchronization of frame sync B with external
frame sync.
0 = Frame sync disabled
1 = Frame sync enabled
17 CLKB_SYNC Enable synchronization of clock B with external frame
sync.
0 = Clock disabled
1 = Clock enabled
18 CLKB_SOURCE_IOP Enable clock B input source.
0 = XTAL buffer output selected for clock B
1 = EXT_CLKA_I selected for clock B
19 FSB_SOURCE_IOP Enable frame sync B input source.
0 = XTAL buffer output selected for frame sync B
1 = EXT_CLKA_I selected for frame sync B