ADSP-21368 SHARC Processor Hardware Reference 13-23
Precision Clock Generators
PCG Channel A and B Output Example
Listing 13-3 uses two PCG channels. Channel A is set up to only generate
a clock signal. This clock signal is used as the input to channel B through
SRU1. The clock and frame sync are routed to DAI pins 1 and 2, respec-
tively, in the same manner as Listing 13-1. The frame sync generated in
this example is set for a 50% duty cycle, with no phase shift.
Listing 13-3. PCG Channel A and B Output Example
/* Register Definitions */
#define SRU_CLK4 0x2434
#define SRU_PIN0 0x2460
#define SRU_PBEN0 0x2478
#define PCG_CTLA0 0x24C0
#define PCG_CTLA1 0x24C1
#define PCG_CTLB0 0x24C2
#define PCG_CTLB1 0x24C3
#define PCG_PW 0x24C4
/* SRU Definitions */
#define PCG_CLKA_O 0x1c
#define PCG_CLKB_P 0x39
#define PCG_FSB_P 0x3B
#define PBEN_HIGH_Of 0x01
//Bit Positions
#define PCG_EXTB_I 5
#define DAI_PB02 7
#define DAI_PBE02 6
#define PCG_PWB 16
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