Programming Examples
13-24 ADSP-21368 SHARC Processor Hardware Reference
/* Bit Definitions */
#define ENCLKA 0x80000000
#define ENFSB 0x40000000
#define ENCLKB 0x80000000
#define CLKBSOURCE 0x80000000
#define FSBSOURCE 0x40000000
/* Main code section */
.global _main; /* Make main global to be accessed by ISR */
.section/pm seg_pmco;
_main:
/*Route PCG Channel A clock to PCG Channel B Input via SRU*/
r0 = (PCG_CLKA_O<<PCG_EXTB_I);
dm(SRU_CLK4) = r0;
/* Route PCG Channel B clock to DAI Pin 1 via SRU */
/* Route PCG Channel B frame sync to DAI Pin 2 via SRU */
r0 = (PCG_CLKB_P|(PCG_FSB_P<<DAI_PEB02));
dm(SRU_PIN0) = r0;
/* Enable DAI Pins 1 & 2 as outputs */
r0 = (PBEN_HIGH_Of|(PBEN_HIGH_Of<<DAI_PB02));
dm(SRU_PBEN0) = r0;
r0 = ENCLKA; /* Enable PCG Channel A Clock, No Channel A FS */
/* FS Divisor = 0, FS Phase 10-19 = 0 */
dm(PCG_CTLA0) = r0;
r1 = 0xfffff; /* Clk Divisor = 0xfffff, FS Phase 0-9 = 0 */
/* Use CLKIN as clock source */
dm(PCG_CTLA1) = r1;
r0 = (5<<PCG_PWB); /* PCG Channel B FS Pulse width = 1 */
dm(PCG_PW) = r0;
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