Analog Devices SHARC ADSP-21368 - Page 591

ADSP-21368 SHARC Processor Hardware Reference 13-25
Precision Clock Generators
r0 = (ENFSB|ENCLKB|10); /*Enable PCG Channel B Clock and FS*/
/* FS Divisor = 10, FS Phase 10-19 = 0 */
dm(PCG_CTLB0) = r0;
r0 = (CLKBSOURCE|FSBSOURCE|10); /* Clk Divisor = 10 */
/* FS Phase 0-9 = 0, Use SRU_MISC4 as clock source */
dm(PCG_CTLB1) = r0;
_main.end: jump(pc,0);