SPORT Operation Modes
5-14 ADSP-21368 SHARC Processor Hardware Reference
details on this option. Similar to the serial clock, the frame sync can be an
external signal or generated internally. The
IFS bit in the SPCTL register
allows the selection between these options (see the internal frame sync
select bit description in Figure 5-10 on page 5-70 for more details). For
internally-generated frame syncs, the FSDIV bits in the DIVx register con-
figure the frame sync rate. For internally-generated frame syncs, it is also
possible to configure whether the frame sync signal is activated based on
the FSDIV setting and the transmit or receive buffer status, or by the FSDIV
setting only.
All settings are configured through the DIFS bit of the SPCTL register. See
“Data-Independent Frame Syncs” on page 5-41 for more details. The
frame sync can be configured to be active high or active low through the
LFS bit in the SPCTL register. See “Active Low Versus Active High Frame
Syncs” on page 5-39 for more details). The timing between the frame sync
signal and the first bit of data that are either transmitted or received is also
selected through the LAFS bit in the SPCTL register. See “Early Versus Late
Frame Syncs” on page 5-40 for more details.
Data Formatting
Several data formatting options are available for the SPORTs in DSP stan-
dard serial mode. Each SPORT has an A and B channel available. Both
can be configured for transmitting or receiving. The SPTRAN bit controls
the configuration of transmit versus receive operations. Serial ports can
transmit or receive a selectable word length, which is programmed by the
SLEN bits in the SPCTL register (see “Setting Word Length (SLEN)” on
page 5-17 for more details).
Serial ports also include companding hardware built into the A channels
that allows sign extension or zero-filling of upper bits of the serial data
word. These configurations are selected by the DTYPE bits in the SPCTL reg-
ister. See “Data Type” on page 5-46 and “Companding” on page 5-47 for
more information.
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