ADSP-21368 SHARC Processor Hardware Reference 5-49
Serial Ports
With companding enabled, interfacing the SPORT to a codec requires lit-
tle additional programming effort. If companding is not selected, two
formats are available for received data words of fewer than 32 bits—one
that fills unused MSBs with zeros, and another that sign-extends the MSB
into the unused bits.
SPORT Control Registers and Data Buffers
The ADSP-21367/8/9 and ADSP-2137x processors have up to eight
SPORTs. Each SPORT has two data paths corresponding to channel A
and channel B. These data buffers are TXSPxA and RXSPxA (primary) and
TXSPxB and RXSPxB (secondary). Channel A and B in all eight SPORTS
operate synchronously to their respective SPORTx_CLK and SPORTx_FS sig-
nals. Companding is supported only on primary A channels.
The registers used to control and configure the SPORTs are part of the
IOP register set. Each SPORT has its own set of 32-bit control registers
and data buffers. The SPORT registers are described in Table 5-5 through
Table 5-8.
The SPORT control registers are programmed by writing to the appropri-
ate address in memory. The symbolic names of the registers and individual
control bits can be used in programs. The definitions for these symbols are
contained in the file
def21367.h located in the INCLUDE directory of the
ADSP-21xxx DSP development software. All control and status bits in the
SPORT registers are active high unless otherwise noted.
Since the SPORT registers are memory-mapped, they cannot be written
with data directly. Instead, they must be written from (or read into) pro-
cessor core registers, usually one of the general-purpose universal registers
(
R0–R15) of the register file or one of the general-purpose universal status
registers (
USTAT1–USTAT4).
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