ADSP-21368 SHARC Processor Hardware Reference A-17
Register Reference
AMI Control Registers (AMICTLx)
The AMICTL0–3 registers control the mode of operations for the four banks
of external memory. These registers are shown in Figure A-6 and
described in Table A-5.
Figure A-6. AMICTLx Registers
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AMIEN
IC
HC
Bus Hold Cycle (at end of write access)
000=Disable bus hold cycle
001=Hold address for 1 EP cycle
010=Hold address for 2 EP cycles
WS
Wait States
00000=Reserved
00001=Reserved
00010=Wait state = 2
...
11111=Wait state = 31
BW
External Data Bus Width
00=8-bit
01=16-bit
10=32-bit
11=Reserved
AMI Enable
1=Enable
0=Disable
PKDIS
Packing/Unpacking Disable
1=8/16-bit data zero-filled
0=8/16 bit data packed to
32-bit data
MSWF
Most Significant Word First
1=1st 8/16-bit word occupies the most significant position in 32-bit packed word
0=1st 8/16-bit word occupies the least significant position in the 32-bit packed word
ACKEN
ACK Pin Enable
1=Enable ACK pin
0=Disable ACK pin
AMICTL0 (0x1804)
AMICTL1 (0x1805)
AMICTL2 (0x1806)
AMICTL3 (0x1807)
31 30 29 28 27 26 24 23 22 21 20 19 18 17 16
0000000000000000
RHC
Read Hold Cycle
000=Disable read hold cycle
001=Hold address for 1 EP clock cycle
010=Read hold cycle 2
IC
Bus Idle Cycle
000=0 cycles, 001=1 cycle
010=2 cycles, 011=3 cycles
100=4 cycles, 101=5 cycles
110=6 cycles, 111=7 cycles
NO_OPT
Disable Predictive Reads
1=Disable predictive reads
0=Default, predictive reads are enabled
FLSH
AMI Buffer Flush
1=Flush buffer
0=Buffer holds data
Reserved
25
0000000000000000
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