External Port Registers
A-16 ADSP-21368 SHARC Processor Hardware Reference
12 CHS DMA Chaining Status (read-only).
0 = DMA chain loading is not active
1 = DMA chain loading is active
13 TLS Tap List Loading Status (read-only).
0 = Tap list loading is not active
1 = Tap list loading is active
14 WBS Delay Line Write Pointer Write Back Status (read-only).
0 = Write pointer write back is not active
1 = Write pointer write back is active
15 EXTS DMA External Interface Status (read-only).
0 = DMA external interface does not have any access pending
1 = DMA external interface has access pending
16 DIRS DMA Transfer Direction Status (read-only).
0 = DMA direction is external reads
1 = DMA direction is external writes
Note: This is useful for delay line DMA where the transfer direc-
tion changes with the state of the DMA state machine.
For normal DMA, DIRS will reflect the state of the DMADR
bit.
31–17 Reserved
Table A-4. External Port DMA Register Bit Descriptions (Cont’d)
Bit Name Description
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