ADSP-21368 SHARC Processor Hardware Reference 8-15
Pulse Width Modulation
Update Modes
Update modes determine the frequency with which the waveforms are
sampled.
Single Update
In this mode, duty cycle values are programmable only once per PWM
period, so that the resultant PWM patterns are symmetrical about the
midpoint of the PWM period.
Double Update
In this mode, a second updating of the PWM registers is implemented at
the midpoint of the PWM period. In this mode, it is possible to produce
asymmetrical PWM patterns that produce lower harmonic distortion in
three-phase PWM inverters. This technique also permits closed-loop con-
trollers to change the average voltage applied to the machine windings at a
faster rate, and so permits faster closed-loop bandwidths to be achieved.
Configurable Polarity
The polarity of the generated PWM signals is programmed using the
PWMPOLARITY3–0 registers (see “PWM Polarity Select Registers (PWM-
POLx)” on page A-83), so that either active high or active low PWM
patterns can be produced. The polarity values can be changed on-the-fly if
required, provided the change is done a few cycles before the next period
change.
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