ADSP-21368 SHARC Processor Hardware Reference 8-19
Pulse Width Modulation
• PWM period registers. The
PWMPERIOD3–0 registers are 16-bit,
read/write registers that control the period of the four PWM
groups.
• PWM dead time registers. The PWMDT3–0 registers are 16-bit,
read/write registers that are used to set the switching dead time.
• PWM channel A and B duty control registers. The PWMA3–0 and
PWMBx registers directly control the duty cycles of the two pairs of
PWM output signals on the pwm_ah to pwm_cl pins when not in
switch reluctance mode.
• PWM output enable registers. The PWMSEG3–0 registers are 16-bit
read/write registers that are used to control the output signals of
the four PWM groups.
• PWM channel A and B low side duty control registers. In
non-paired mode, the PWMAL3–0 and PWMBL3–0 registers are used to
program the low side duty cycle of the two pairs of PWM output
signals. These can be different for the high side cycles.
• PWM output polarity select registers. The PWMPOL3–0 registers are
16-bit read/write registers that are used to determine whether the
polarity of the generated PWM signals are active high or active low.
The polarity values can be changed on-the-fly if required, provided
the change is done a few cycles before the next period change.
Duty Cycles
The PWMAx and PWMBx registers directly control the duty cycles of the two
pairs of PWM output signals on the
pwm_ah to pwm_cl pins when not in
switch reluctance mode.
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