Functional Description
6-2 ADSP-21368 SHARC Processor Hardware Reference
• Programmable baud rates, clock polarities, and phases
• Master or slave booting from a master SPI device (“DPI/SRU2
Connection Groups” on page 4-51)
• DMA capability to allow data transfers without core overhead
Functional Description
Each SPI port contain its own transmit shift (TXSR, TXSRB) and receive
shift (RXSR, RXSRB) registers which are not user accessible. The TXSRx regis-
ters serially transmit data and the RXSRx registers receive data
synchronously with the SPI clock signal (SPICLK). Figure 6-1 shows a
block diagram of the ADSP-21367/8/9 and ADSP-2137x processor’s SPI
interface. The data is shifted into or out of the shift registers on two sepa-
rate pins: the master in slave out (MISO) pin and the master out slave in
(MOSI) pin.
During data transfers, one SPI device acts as the SPI master by controlling
the data flow. It does this by generating the SPICLK and asserting the SPI
device select signal (SPIDS). The SPI master receives data using the MISO
pin and transmits using the MOSI pin. The other SPI device acts as the SPI
slave by receiving new data from the master into its RXSRx register using
the MOSI pin. It transmits requested data out of the TXSR register using the
MISO pin.
Each SPI port contains a dedicated transmit data buffer (TXSPI, TXSPIB)
and a receive data buffer (RXSPI, RXSPIB). Data to be transmitted is writ-
ten to
TXSPIx and then automatically transferred into the TXSR register.
Once a full data word is received in the
RXSR register, the data is automat-
ically transferred into RXSPI, from which the data is read. When the port is
in SPI master mode, programmable flag pins provide slave selection. Con-
nect these pins to the SPIDS of the slave devices.
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