ADSP-21368 SHARC Processor Hardware Reference 4-73
Digital Audio/Digital Peripheral Interfaces
As an example, the output of the clock to DPI pin 3 would be configured
in SPI mode 3 as follows.
SRU(SPI_CLK_O,DPI_PB03_I);
SRU(SPI_CLK_O,DPI_PBEN03_I);
Configuring the Two Wire Interface
Each TWI device, whether master or slave, responds to the other devices
with an acknowledge bit when data is received. For details, see
Chapter 12, Two Wire Interface Controller. For proper operation, the
SRU must be set up so that data communication is possible in both direc-
tions on the data pin.
The examples in Listing 4-1 through Listing 4-4 show the SRU settings
for different TWI modes.
Listing 4-1. TWI Master Transmit Mode
SRU(LOW,DPI_PB11_I) /* Since TWI output is an open-drain
output, the TWI pin is connected
to logic level low */
SRU(TWI_DATA_PBEN_O,DPI_PBEN11_I) /* TWI data output connected
to DPI pin 11 input */
Table 4-14. SPI Pin Enable Selections
Mode CLKPL CPHASE Use Pin Enable...
000HIGH
101HIGH
210SPI_CLK_O
311SPI_CLK_O
To Next Page
Loading...
Need help?
General
