ADSP-21368 SHARC Processor Hardware Reference 3-5
External Port
When an unmasked interrupt occurs and is serviced, program execution
automatically jumps to the location of the corresponding interrupt vector
table in internal memory. Upon returning from the interrupt, the
sequencer resumes execution from external memory because locating the
IVT in external memory is not supported. Placing the interrupt vector
table in external memory is not supported.
Instruction Cache
To circumvent the relative difference in clock domains between the core
and external memory interface (1:2 in the best case) and enable faster exe-
cution throughput, the functionality of the traditional “conflict” cache on
the SHARC has been enhanced to serve as an instruction cache in external
execution mode.
In previous generations of SHARC processors, the function of the conflict
cache had been to cache only those instructions whose fetching conflicted
with access of a data operand from memory over the PM bus. The
enhancements to the cache architecture mean that the functionality of the
cache remains intact for execution from internal memory whereas it
behaves as instruction cache for external memory execution. Every
instruction that is fetched from external memory into the program
sequencer is also simultaneously loaded into the cache. The next time that
this instruction needs to be fetched from external memory, it is first
searched for in the cache. The instruction is stored using the entire 24-bit
address. Figure 3-1 shows the format for storing an instruction and
Figure 3-2 shows the cache architecture.
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