Analog Devices SHARC ADSP-21368 - Page 114

External Memory Interface
3-6 ADSP-21368 SHARC Processor Hardware Reference
Figure 3-1. Cache Operation During Instruction Execution from External
Memory
Figure 3-2. Instruction Cache Architecture
PM Address Bus
DM Address Bus
PM Data Bus
DM Data Bus
Packing
Unit
SDRAM
Controller
Asynchronous
Memory
Interface
PROGRAM
Sequencer
Instruction
Cache
32-bit x 48-bit
16/32*
11
24
Data
Control
Address
24
24
64
64
EXTERNAL PORT
*The external bus is 32 bits on the ADSP-21371 and
16 bits on the ADSP-21375.
INSTRUCTIONS
SET
0
SET
1
SET
2
SET
13
SET
14
SET
15
ADDRESSES
BITS (23-4)
LRU
BIT
VALID
BIT
ENTRY 0
ENTRY 0
ENTRY 0
ENTRY 1
ENTRY 1
ENTRY 1
ENTRY 0
ENTRY 0
ENTRY 0
ENTRY 1
ENTRY 1
ENTRY 1
ADDRESSES
BITS (3-0)
0000
0001
0010
1101
1110
1111