ADSP-21368 SHARC Processor Hardware Reference 12-7
Two Wire Interface Controller
controller appends the read/write bit as appropriate based on the state of
the
MDIR bit in the master mode control register. For more information,
see “Master Address Register (TWIMADDR)” on page A-139.
Master Mode Status Register
The TWI master mode status register (TWIMSTAT) holds information dur-
ing master mode transfers and at their conclusion. Generally, master mode
status bits are not directly associated with the generation of interrupts but
offer information on the current transfer. Slave mode operation does not
affect master mode status bits. This is a read-only register. For more infor-
mation, see “Master Status Register (TWIMSTAT)” on page A-140.
FIFO Control Register
The TWI FIFO control register (TWIFIFOCTL) affect only the FIFO and is
not tied in any way with master or slave mode operation. For more infor-
mation, see “FIFO Control Register (TWIFIFOCTL)” on page A-143.
FIFO Status Register
The fields in the TWI FIFO status register (TWIFIFOSTAT) indicate the
state of the FIFO buffers’ receive and transmit contents. The FIFO buffers
do not discriminate between master data and slave data. By using the sta-
tus and control bits provided, the FIFO can be managed to allow
simultaneous master and slave operation. All bits in this register are
read-only. For more information, see “FIFO Status Register (TWIFIFOS-
TAT)” on page A-145.
Interrupt Source Register
The TWI interrupt source register (TWIIRPTL) contains information about
functional areas requiring servicing. Many of the bits in this register serve
as an indicator to further read and service various status registers.
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