Analog Devices SHARC ADSP-21368 - Peripheral Interrupt Priority0 Control Register (PICR0

ADSP-21368 SHARC Processor Hardware Reference A-167
Register Reference
Peripheral Interrupt Priority0 Control
Register (PICR0)
This 32-bit, read/write register controls programmable peripheral inter-
rupts 0–5 and the default sources shown in Figure A-79. This register is
located at address 0x2200. The reset value of this register is 0x0A418820.
Figure A-79. PICR0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0000000000000000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
P5I
SPI Interrupt
Programmable Interrupt 1
P1I
SPORT5 Interrupt
Programmable Interrupt 5
PICR0 (0x2200)
P4I
SPORT3 Interrupt
Programmable Interrupt 4
P3I
SPORT1 Interrupt
Programmable Interrupt 3
DAI High Priority Interrupt
Programmable Interrupt 0
P0I
General-Purpose IOP Timer0 Interrupt
Programmable Interrupt 2
P2I
RESET=0x0A418820