Setting AMI Modes
3-26 ADSP-21368 SHARC Processor Hardware Reference
For packed data mode where
PKDIS = 0 and MSWF = 1, the packing order
for BW = 8 is: first byte received is bits 31–24, the second byte is bits
23–15, and so on.
If the PKDIS bit is set (=1), then the 8- or 16-bit data (based on the bus
width) is zero appended to 32 bits.
Both of these methods apply to 16- to 32-bit packing as well. These
modes are summarized in Table 3-10.
External Memory Writes
The AMI behaves as an external port bus slave and external write accesses
are performed when there is a write request from the external port control
bus. Writes to external memory are done through the AMI module. When
an external address that is mapped to the AMI in the EPCTL register is
accessed, the module receives data from internal memory using the DMA
Table 3-10. Data Packing Bit Settings (Reads)
Packing
Mode
PKDIS Bit
Setting
MSWF Bit
Setting Description
Enabled 0 0 8- or 16-bit received data is packed to 32-bit data
and transmitted 32-bit data is unpacked to two
16-bit data or four 8-bit data.
First 8- or 16-bit word read/written occupies the
least significant position in the 32bit packed word.
Enabled 0 1 8 or 16 bit received data is packed to 32-bit data
and 32-bit data to be transmitted is unpacked to
two 16-bit data or four 8-bit data.
First 8- or 16-bit word read/written occupies the
most significant position in the 32-bit packed word.
Disabled 1 N/A 8- or 16-bit data received is zero filled. For transmit-
ted data only 16-bit or the 8-bit LSB part of the
32-bit data word is written to external memory.
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