ADSP-21368 SHARC Processor Hardware Reference 9-9
S/PDIF Transmitter/Receiver
In SCDF mode, the transmitter sends successive audio samples of the
same signal across both subframes, instead of channel A and B. This mode
also allows programs to select which channel is sent when using bits in the
S/PDIF transmit control register. The channel status bits are set to pro-
vide the downstream receiver with information about which channel is
used.
Channel Status
In addition to encoding the audio data in the bi-phase format, the trans-
mitter also provides a way to easily add the channel status information to
the outgoing bi-phase stream. There are status registers in the transmitter
that correspond to each channel or subframe. Byte 0 for each channel A
and B reside in the DITCTL register, and bytes 1–4 reside in the DITCHANxx
registers. For more information, see “Transmitter Control Register
(DITCTL)” on page A-86, “Left Channel Status for Subframe A Registers
(DITCHANAx)” on page A-89 and “Right Channel Status for Subframe
B Registers (DITCHANBx)” on page A-90.
The first five bytes of the channel status may be written all at once to the
control registers for both A and B channels. As the data is serialized and
transmitted, the appropriate bit is inserted into the channel status area of
the 192-word frame. Validity bits for both channels may also be con-
trolled by the transmitter control register. Optionally, the user bit, validity
bit, and channel status bit are sent to the transmitter with each left/right
sample. For each subframe the parity bit is automatically generated and
inserted into the bi-phase encoded data. A mute control and support for
double-frequency single-channel mode are also provided. The serial data
input format may be selected as left-justified, I
2
S, or right-justified with
16-, 18-, 20- or 24-bit word widths. The over sampling clock is also
selected by the transmitter control register.
To Next Page
Loading...
Need help?
General
