ADSP-21368 SHARC Processor Hardware Reference 14-33
System Design
RESET Input Hysteresis
Hysteresis is used only on the RESET input signal. Hysteresis causes the
switching point of the input inverter to be slightly above 1.4 V for a rising
edge and slightly below 1.4 V for a falling edge. The value of the hysteresis
is approximately ± 0.1 V. The hysteresis is intended to prevent multiple
triggering of signals which are allowed to rise slowly, as might be expected
on a reset line with a delay implemented by an RC input circuit. Hystere-
sis is not used to reduce the effect of ringing on processor input signals
with fast edges, because the amount of hysteresis that can be used on a
CMOS chip is too small to make a difference. The small amount of hys-
teresis allowable is due to the restrictions on the tolerance of the V
IL
and
V
IH
TTL input levels under worst-case conditions. Refer to the prod-
uct-specific processor data sheet for exact specifications.
Designing for High Frequency Operation
Because the processor must be able to operate at very high clock frequen-
cies, signal integrity and noise problems must be considered for circuit
board design and layout. The following sections discuss these topics and
suggest various techniques to use when designing and debugging target
systems.
All synchronous processor behavior is specified to CLKIN. System designers
are encouraged to clock synchronous peripherals with this same clock
source (or a different low-skew output from the same clock driver).
Clock Specifications and Jitter
The clock signal must be free of ringing and jitter. Clock jitter can easily
be introduced into a system where more than one clock frequency exists.
Jitter should be kept to an absolute minimum. High frequency jitter on
the clock to the processor may result in abbreviated internal cycles.
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