S/PDIF Receiver
9-16 ADSP-21368 SHARC Processor Hardware Reference
S/PDIF Receiver
The S/PDIF receiver is compliant with all common serial digital audio
interface standards including IEC-60958, IEC-61937, AES3, and AES11.
These standards define a group of protocols that are commonly associated
with the S/PDIF interface standard defined by AES3, which was devel-
oped and is maintained by the Audio Engineering Society. AES3
effectively defines the data and status bit structure of an S/PDIF stream.
AES3-compliant data is sometimes referred to as AES/EBU compliant.
This term highlights the adoption of the AES3 standard by the European
Broadcasting Union. The S/PDIF receiver in the ADSP-21367/8/9 and
ADSP-2137x processors receives an S/PDIF bi-phase encoded stream and
decodes it into an I
2
S serial data format, and provides the programmer
with several methods of managing the incoming status bit information.
The input to the receiver is a bi-phase encoded signal that may contain
two audio channels (compressed or linear PCM) or non-audio data. The
receiver decodes the single bi-phase encoded stream, producing an
I
2
S-compatible serial data output that consists of a serial clock (SCLK), a
left/right clock (FS), and data (channel A/B).
The receiver can recover the clock from the bi-phase encoded stream using
either a dedicated on-chip digital phased-locked loop (PLL) or an external
analog PLL. (The dedicated on-chip digital PLL is separate from the PLL
that supplies the core clock to the ADSP-213xx processor core.)
The S/PDIF receiver input stream can be selected from any of the DAI
pins, DAI_P20–1, or from the output of the S/PDIF transmitter for
loop-back testing using signal routing group C. The first five bytes of the
channel status are identified and stored in dedicated status registers for
both A and B channels. The registers are DIR_CHANL and DIR_CHANR. As the
serial data is received, the appropriate bits (first five bytes – bit 0 through
bit 39) are updated from the 192-word frame. If the channel status bits
change, an interrupt may optionally be generated to notify the core.
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