ADSP-21368 SHARC Processor Hardware Reference 9-5
S/PDIF Transmitter/Receiver
Channel status information is organized in 192-bit blocks, subdi-
vided into 24 bytes. The first bit of each block is carried in the
frame with preamble Z.
For convenience, the first five bytes of the channel status may be
written all at once to control registers for both channels A and B
(
SPDIF_TX_CTL, SPDIF_TX_CHSTA, and SPDIF_TX_CHSTB). If the
CHST_BUF_ENABLE bit is set in the SPDIF_TX_CTL register, the appro-
priate CS bit is ORed into the channel status bit of the 192-word
frame. In addition, the CS bit can also be provided along with the
data samples to be transmitted.
4. Parity bit (time slot 31). The parity bit indicates that time slots 4
to 31 inclusive will carry an even number of ones and an even
number of zeros (even parity). The parity bit is automatically gen-
erated for each subframe and inserted into the encoded data.
The two subframes in a frame can be used to transmit two channels of
data (channel 1 in subframe 1, channel 2 in subframe 2) with a sample
rate equal to the frame rate. Alternatively, the two subframes can carry
successive samples of the same channel of data, but at a sample rate that is
twice the frame rate. This is called single-channel, double-frequency
(SCDF). For more information, see “Single-Channel, Double-Sampling
Frequency Mode” on page 9-21.
Channel Coding
To minimize the direct-current (dc) component on the transmission line,
to facilitate clock recovery from the data stream, and to make the interface
insensitive to the polarity of connections, time slots 4 to 31 are encoded in
bi-phase mark.
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