Analog Devices SHARC ADSP-21368 User Manual (English)

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Programming Examples

13-20 ADSP-21368 SHARC Processor Hardware Reference

/* Enable PCGA SCLK & FSYNC and set FSYNC_A divisor */

r0 = (ENCLKA | ENFSA | PCGA_FS_DIVISOR);

dm(PCG_CTLA0) = r0;

/* Set PCGB SCLK & FSYNC Source first to Xtal Buffer and set

SCLK_B divisor */

r0 = ((PCGB_FS_PHASE_LO << 20) | PCGB_CLK_DIVISOR);

dm(PCG_CTLB1) = r0;

/* Enable PCGB SCLK and disable FSYNC_B */

r0 = (ENCLKB | ENFSB | PCGB_FS_DIVISOR);

dm(PCG_CTLB0) = r0;

ustat1 = dm(PCG_CTLB0);

bit clr ustat1 ENFSA;

dm(PCG_CTLB0) = ustat1;

/* Set FSYNC_A and FSYNC_B Pulse Width to 50% Duty Cycle

(default) */

r0 = 0x00000000;

dm(PCG_PW) = r0;

dm(PCG_SYNC) = r0;

Init_PCG.end:

rts;

Clock and Frame Sync Divisors PCG Channel B

This section provides two programming examples written for the

ADSP-21369 processor. The first listing, Listing 13-2, uses PCG channel

B to output a clock on DAI pin 1 and frame sync on DAI pin 2. The input

used to generate the clock and frame sync is CLKIN. This example demon-

strates the clock and frame sync divisors, as well as the pulse width and

phase shift capabilities of the PCG.

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Analog Devices SHARC ADSP-21368 Specifications

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