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ADSP-21368 SHARC Processor Hardware Reference 13-19

Precision Clock Generators

Listing 13-1. PCG Initialization

/***********************************************************

Required Output Sample Rate = 65.098 kHz

Function Control Reg Phase/ Reg Hex

reg Address Divisor Contents

FS_A_Ph_Hi/FS_A_Div PCG_CTLA0 0x24C0 0/512 0xC00/00200

FS_A_Ph_Lo/CLK_A_Div PCG_CTLA1 0x24C1 4/8 0x004/00008

--------------------------------------------------------------

FS_B_Ph_Hi/FS_B_Div PCG_CTLB0 0x24C2 -/- 0x800/00000

FS_B_Ph_Lo/CLK_B_Div PCG_CTLB1 0x24C3 0/2 0x000/00002

PW_FS_B/PW_FS_A PCG_PW 0x24C4 0/0 0x0000:0000

**************************************************************/

#include <def21369.h>

/* PCGA --> SCLK & FSYNC Divisors, Sample Rate = 65.098 kHz */

#define PCGA_CLK_DIVISOR 0x0008 /* SCLK output = Fs */

#define PCGA_FS_DIVISOR 0x0200 /* FSYNC output = 64xFs */

#define PCGA_FS_PHASE_LO 0x04 /* Set FSYNC/SCLK Phase for

digital audio IF mode */

PCGB --> PCG_CLKx_O Divisor

#define PCGB_CLK_DIVISOR 0x0002 /* PCG_CLKx_O output =

256xFs */

#define ENCLKA 0x80000000

#define ENFSA 0x40000000

#define PCGB_FS_DIVISOR 0x0000 /* Not used - disabled */

#define PCGB_FS_PHASE_LO 0x00 /* Don’t care */

.section/pm seg_pmco; .global Init_PCG;

/***********************************************************/

Init_PCG:

/* Set PCGA SCLK & FSYNC Source first to Xtal Buffer and set

SCLK_A divisor */

r0 = ((PCGA_FS_PHASE_LO << 20) | PCGA_CLK_DIVISOR);

dm(PCG_CTLA1) = r0;

Analog Devices SHARC ADSP-21368 User Manual

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