Theory of Operation
10-2 ADSP-21368 SHARC Processor Hardware Reference
multiplexing (TDM) mode for daisy-chaining multiple SRCs to a proces-
sor. The serial output data is dithered down to 20, 18, or 16 bits when
20-, 18-, or 16-bit output data is selected.
Theory of Operation
The SRC sample rate converts the data from the serial input port to the
sample rate of the serial output port. The sample rate at the serial input
port can be asynchronous with respect to the output sample rate of the
output serial port.
Conceptually, the SRC interpolates the serial input data by a rate of 2
20
and samples the interpolated data stream by the output sample rate. In
practice, a 64-tap FIR filter with 2
20
poly phases, a FIFO, a digital-servo
loop that measures the time difference between the input and output sam-
ples within 5 ps, and a digital circuit to track the sample rate ratio are used
to perform the interpolation and output sampling. The digital-servo loop
and sample rate ratio circuit automatically track the input and output
sample rates.
The digital-servo loop measures the time difference between the input and
output sample rates within 5 ps. This is necessary in order to select the
correct polyphase filter coefficient. The digital-servo loop has excellent jit-
ter rejection for both input and output sample rates as well as the master
clock. The jitter rejection begins at less than 1 Hz. This requires a long
settling time whenever the SRC is enabled or when the input or output
sample rate changes.
To reduce the settling time when the SRC is enabled or there is a change
in the sample rate, the digital-servo loop enters the fast settling mode.
When the digital-servo loop has adequately settled in the fast mode, it
switches into the normal or slow settling mode and continues to settle
until the time difference measurement between input and output sample
rates is within 5 ps. During fast mode, the MUTE_OUT signal is asserted high.
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