ADSP-21368 SHARC Processor Hardware Reference 10-3
Asynchronous Sample Rate Converter
Normally, the
MUTE_OUT signal is connected to the MUTE_IN signal. The
MUTE_IN signal is used to softly mute the SRC upon assertion and softly
stop muting the SRC when it is deasserted.
The sample rate ratio circuit is used to scale the filter length of the FIR fil-
ter for decimation. Hysteresis in measuring the sample rate ratio is used to
avoid oscillations in the scaling of the filter length, which would cause dis-
tortion on the output.
However, when multiple SRCs are used with the same serial input port
clock and the same serial output port clock, the hysteresis causes different
group delays between multiple SRCs. A phase-matching mode feature was
added to the SRC to address this problem. In phase-matching mode, one
SRC, (the master), transmits its sample rate ratio to the other SRCs, (the
slaves), so that the group delay between the multiple SRCs remains the
same.
Asynchronous sample rate conversion is converting data from one clock
source at a sample rate to another clock source at the same or a different
sample rate. The simplest approach to an asynchronous sample rate con-
version is the use of a zero-order hold between the two samplers shown in
Figure 10-1. In the figure, f
S_IN
and f
S_OUT
are the input and output
sampling frequencies, respectively, and T1 and T2 are the time periods
that correspond to the input and output. In an asynchronous system, T2
is never equal to T1 nor is the ratio between T2 and T1 rational. As a
result, samples at f
S_OUT
are repeated or dropped, thus producing an error
in the resampling process. The frequency domain shows the wide side
lobes that result from this error when the sampling of f
S_OUT
is convolved
with the attenuated images from the sin(x)/x nature of the zero-order
hold. The images at f
S_IN
, (dc signal images), of the zero-order hold are
infinitely attenuated. Since the ratio of T2 to T1 is an irrational number,
the error resulting from the resampling at f
S_OUT
can never be eliminated.
However, the error can be significantly reduced through interpolation of
the input data at f
S_IN
. The SRC is conceptually interpolated by a factor
of 2
20
.
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