Phase Shift
13-10 ADSP-21368 SHARC Processor Hardware Reference
L
When using a clock and frame sync as a synchronous pair, the units
must be enabled in a single atomic instruction before their parame-
ters are modified. Both units must also be disabled in a single
atomic instruction.
Phase Shift Settings
The phase shift between clock and frame sync outputs may be pro-
grammed under these conditions:
• The input clock source for the clock generator output and the
frame sync generator output is the same.
• Clock and frame sync are enabled at the same time using a single
atomic instruction.
• Frame sync divisor is an integral multiple of the clock divisor.
If the phase shift is 0, the clock and frame sync outputs rise at the same
time. If the phase shift is 1, the frame sync output transitions one input
clock period ahead of the clock transition. If the phase shift is
divisor – 1, the frame sync transitions divisor – 1 input clock periods
ahead of the clock transitions. This translates to the one input clock
period after the clock transition (Figure 13-3).
Phase shifting is represented as a full 20-bit value so that even when frame
sync is divided by the maximum amount, the phase can be shifted to the
full range, from zero to one input clock short of the period.
Pulse Width
Pulse width is the number of input clock periods for which the frame sync
output is high. Pulse width should be less than the divisor of the frame
sync. The pulse width of frame sync A is specified in the PWFSA bits (15–0)
of the PCG_PW register and the pulse width of frame sync B is specified in
the
PWFSB bits (31–16) of the PCG_PW register. Similarly, the pulse width of
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