ADSP-21368 SHARC Processor Hardware Reference A-3
Register Reference
When there is contention among the buses for access to registers in the
same I/O processor register group, the processor arbitrates register access
as follows:
• Data memory (DM) bus accesses
• Program memory (PM) bus accesses
• I/O processor (IO) bus (lowest priority) accesses
The bus with highest priority gets access to the I/O processor register
group, and the other buses are held off from accessing that I/O processor
register group until that access has been completed.
Since the I/O processor registers are memory-mapped, the processor’s
architecture does not allow programs to directly transfer data between
these registers and other memory locations, except as part of a DMA oper-
ation. To read or write I/O processor registers, programs must use the
processor core registers.
The register names for I/O processor registers are not part of the proces-
sor’s assembly syntax. To ease access to these registers, programs should
use the header file containing the registers’ symbolic names and addresses.
Notes on Reading Register Drawings
The register drawings in this appendix provide “at a glance” information
about the register in question. They are designed to give experienced users
basic information about a register and its bits. When using these registers,
the following should be noted.
1. The register name and address are provided in the upper left-hand
corner of the drawing.
2. The bit settings in the drawings represent their state at reset.
To Next Page
Loading...
Need help?
General
