ADSP-21368 SHARC Processor Hardware Reference 14-13
System Design
If the
TRST pin is not asserted (or held low) at power-up, the JTAG port is
in an undefined state that may cause the processor to drive out on I/O
pins that would normally be three-stated at reset. The TRST pin can be
held low with a jumper to ground on the target board connector.
A detailed discussion of JTAG and its uses can be found in Engi-
neer-to-Engineer Note EE-68, Analog Devices JTAG Emulation Technical
Reference. This document is available on the Analog Devices Web site at
www.analog.com/processors.
Clock Derivation
The processor uses a PLL (phased-locked loop) to provide clocks that
switch at higher frequencies than the system clock (CLKIN). The PLL-based
clocking methodology used on the ADSP-21367/8/9 and ADSP-2137x
processors influences the clock frequencies and behavior for the serial,
SPI, and external ports, in addition to the processor core and internal
memory. In each case, the processor PLL provides a non-skewed clock to
the core, internal memory, port logic and I/O pins.
The PLL provides a clock that switches at the processor core frequency to
the serial ports. Each of the serial ports can be programmed to operate at
clock frequencies derived from this clock. The six serial ports’ transmit
and receive clocks are divided down from the processor core clock fre-
quency by setting the
DIVx registers appropriately.
On power-up, the
CLKCFG1–0 pins are used to select ratios of 32:1, 16:1,
and 6:1. After booting, numerous other ratios (slowing or speeding up the
clock) can be selected through software control.
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