ADSP-21368 SHARC Processor Hardware Reference 3-3
External Port
L
External memory address space is supported in normal word
addressing mode only. Single-instruction, multiple-data (SIMD),
extended-precision, short word and long word addressing modes
are not supported. Program execution from external memory on
the ADSP-2136x processors is also not supported.
External Memory Interface on the ADSP-2137x
Processors
The ADSP-2137x SHARC processors support direct execution of instruc-
tions from external memory, using the 16-bit external port (on the
ADSP-21375) or the 32-bit external port (as on the ADSP-21371). Exe-
cution is supported from external memory bank0 space which is selected
by MS0. This external memory can either be SDRAM, or asynchronous
memory, such as SRAM or flash.
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While 16-bit to 48-bit packing, and 32-bit to 48-bit packing are
supported when the external memory is SDRAM, the external
asynchronous memory interface (AMI) also supports 8-bit to
48-bit, 16-bit to 48-bit, and 32-bit to 48-bit instruction packing.
Direct Execution of Instructions From External Memory
While the earlier SHARC processor families (including ADSP-2126x and
ADSP-2136x) supported data storage in external memory, and core as well
as DMA accesses to and from external memory, the ADSP-2137x proces-
sors extends this capability to support direct execution of instructions
from external memory.
Throughput and Instruction Execution Rate
Since instructions on the SHARC processor are 48 bits wide, instruction
throughput when executing code from external SDRAM memory is 2
instructions every 3 SDCLK (peripheral) clock cycles over a 32-bit wide
external port, and 2 instructions every 6 SDCLK clock cycles over a 16-bit
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