ADSP-21368 SHARC Processor Hardware Reference 5-17
Serial Ports
Setting the Internal Serial Clock and Frame Sync Rates
The serial clock rate for internal clocks can be set using the
CLKDIV bit
field in the DIVx register and the frame sync rate for internal frame sync
can be set using the FSDIV bit field in the DIVx register. For details, see
Figure 5-10 on page 5-70.
Left-Justified Sample Pair Mode Control Bits
Several bits in the SPCTLx control register enable and configure left-justi-
fied sample pair mode operation:
• Operation mode (OPMODE)
• Channel enable (SPEN_A and SPEN_B)
• Word length (SLEN)
• Left channel first (FRFS)
• Master mode enable (MSTR)
• Late frame sync (LAFS)
For complete descriptions of these bits, see “SPORT Serial Control Regis-
ters (SPCTLx)” on page A-29.
Setting Word Length (SLEN)
SPORTs handle data words containing 8 to 32 bits in left-justified sample
pair mode. Programs need to set the bit length for transmitting and receiv-
ing data words. For details, see “Word Length” on page 5-43.
The transmitter sends the MSB of the next word in the same clock cycle as
the word select (
SPORTx_FS) signal changes.
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