S/PDIF Transmitter
9-12 ADSP-21368 SHARC Processor Hardware Reference
S/PDIF Transmitter Registers
The SPDIF transmitter contains registers that are used to enable/disable
the transmitter, to manage its operation, and to report status. The regis-
ters are described below.
• DITCTL is the S/PDIF transmit control register. This 32-bit
read/write register is located at address 0x24A0. It is used to enable
the transmitter, control mute, over sampling, mode and data for-
mat. This register is described in detail in “Transmitter Control
Register (DITCTL)” on page A-86.
• DITCHANAx and DITCHANBx are the S/PDIF channel A and
B transmit status registers. These 32-bit read/write registers,
located at addresses 0x24A1 and 0x24A2, provide status informa-
tion for transmitter subframe A and B. These registers are
described in detail in “Left Channel Status for Subframe A Regis-
ters (DITCHANAx)” on page A-89 and “Right Channel Status for
Subframe B Registers (DITCHANBx)” on page A-90. These regis-
ters are used in standalone mode only.
• DITUSRBITAx and DITUSRBITBx are the user bit buffers.
Once programmed, they are used only for the next block of data.
This allows programs to change the user bit information with every
block of data. After writing to the appropriate registers to change
the user bits for the next block, DITUSRBITAx and DITUSRBITBx
must be written to enable the use of these bits. These registers are
used in standalone mode only.
Modes of Operation
The SPDIF transmitter can operate in standalone and full serial modes.
The following sections describe these modes in detail.
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