SPORT Operation Modes
5-22 ADSP-21368 SHARC Processor Hardware Reference
Several bits in the
SPCTLx register control register enable and configure I
2
S
operation:
• Operation mode enable (OPMODE)
• Channel enable (SPEN_A or SPEN_B)
• Word length (SLEN)
•I
2
S channel transfer order (FRFS)
• Master mode enable (MSTR)
•DMA enable (SDEN_A and SDEN_B)
• DMA chaining enable (SCHEN_A and SCHEN_B)
Setting the OPMODE bit = 1 selects the I
2
S mode of operation.
Setting Word Length (SLEN)
SPORTs handle data words containing 8 to 32 bits in standard I
2
S mode.
Programs need to set the bit length for transmitting and receiving data
words. For details, see “Word Length” on page 5-43.
L
More than 32-bit words can be handled using the packed I2S
mode. For more information, see “Packed I2S Mode” on
page 5-33.
The transmitter sends the MSB of the next word one clock cycle after the
word select (FS) signal changes.
In I
2
S mode, load the FSDIV value in the in the DIVx register with the same
value used for SLEN to transmit or receive words continuously. For exam-
ple, for 8-bit data words where
SLEN = 7, set FSDIV = 7.
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