External Memory Interface
3-2 ADSP-21368 SHARC Processor Hardware Reference
External Memory Interface
The external memory interface provides a glueless interface to external
memories. The processor’s I/O processor (IOP) supports synchronous
DRAMs (SDRAMs), SRAMs, FIFOs, flash memory, and ASIC/FPGA
devices. The external memory interface and the SDRAM memory that
interfaces to the external port is clocked by the SDRAM clock (SDCLK).
The ratio of core clock (CCLK) to SDCLK is determined by programming bits
in the power management control (PMCTL) registers. For more informa-
tion, see “Power Management Control Register (PMCTL)” in
Appendix A, Register Reference.
The various possible SDRAM clock to core clock frequency ratios are 1:2,
1:2.5, 1:3, 1:3.5, and 1:4. This ratio is independent of the peripheral
clock (PCLK) used by the other peripherals. For more information on tim-
ing, see Chapter 14, System Design and the appropriate ADSP-21367/8/9
and ADSP-2137x processor data sheet.
The asynchronous external interface follows the standard asynchronous
SRAM access protocol. Programmable wait states, idle cycles, and hold
cycles are provided to interface memories that have different access times.
To extend access, an acknowledge (ACK) signal can be pulled low by the
external device.
The external memory interface supports access to the external memory by
direct core accesses and DMA accesses. The external memory address
space for non-SDRAM addresses is shown in Table 3-1 on page 3-10. The
external memory address space for SDRAM addresses is shown in
Table 3-20 on page 3-52. The external memory is divided in to four
banks. Any bank can be programmed as either asynchronous or synchro-
nous memory.
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