ADSP-21368 SHARC Processor Hardware Reference 6-5
Serial Peripheral Interface Ports
The
SPICLK signal is a gated clock that is active only during data transfers,
and only for the duration of the transferred word. The number of active
edges is equal to the number of bits driven on the data lines. The clock
rate can be as high as one-fourth the peripheral clock rate.
1
For master
devices, the clock rate is determined by the 15-bit value of the baud rate
registers (SPIBAUD, SPIBAUDB). For more information, see “SPI Baud Rate
Registers (SPIBAUD, SPIBAUDB)” on page A-60. For slave devices, the
value in the SPIBAUDx register is ignored. When the SPI device is a master,
SPICLK is an output signal. When the SPI is a slave, SPICLK is an input sig-
nal. Slave devices ignore the serial clock if its device select (SPIDS) signal is
deasserted (HIGH).
Data is shifted in reference to SPICLK. The data is always shifted out on
one edge of the clock (referred to as the active edge) and sampled on the
opposite edge of the clock (referred to as the sampling edge). Clock polar-
ity and clock phase relative to data are programmable through bit 11
(CLKPL) and bit 10 (CPHASE) in the SPICTLx control registers.
SPICLK Timing
When the processor is configured as an SPI slave, the SPI master must
drive an SPICLK signal that conforms with Figure 6-3. For exact timing
parameters, please refer to the appropriate data sheet.
The SPIDS lead time (T1), the SPIDS lag time (T2), and the sequential
transfer delay time (T3) must always be greater than or equal to one-half
the
SPICLK period. The minimum time between successive word transfers
(T4) is two
SPICLK periods. This time period is measured from the last
active edge of SPICLK of one word to the first active edge of SPICLK of the
next word. This calculation is independent from the configuration of the
SPI (
CPHASE, SPIMS, and so on).
1
For complete information on device clock signals and timing, see the processor-specific data sheet.
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